The present invention relates to a semiconductor integrated circuit device including an electrostatic discharge (ESD) protection circuit. In recent years, the degree of integration of a semiconductor integrated circuit device has been increasing along with the technical advancements in the manufacturing process, i.e., a reduction in size and an increase in density. Along with this, such a device has become more vulnerable to damages caused by an electrostatic discharge (hereinafter referred to as a xe2x80x9csurgexe2x80x9d). There are increased possibilities that an element such as an input circuit, an output circuit, an input/output circuit or an internal circuit is broken, or the characteristics thereof are deteriorated, by a surge entering through an external connection pad, for example. Therefore, the external connection pad is often provided with a protection circuit for protecting the input circuit, the output circuit, the input/output circuit or the internal circuit from a surge.
FIG. 7 is an electric circuit diagram illustrating a configuration of an output circuit and other elements around the output circuit in a conventional semiconductor integrated circuit device including an electrostatic discharge protection circuit. As illustrated in FIG. 7, the semiconductor integrated circuit device includes an external connection pad 101, an electrostatic discharge protection circuit 102, an output circuit 103, an output pre-buffer circuit 104, and an internal circuit 121, and is configured so that the output circuit 103 is protected by the electrostatic discharge protection circuit 102 from a surge entering through the external connection pad 101.
The electrostatic discharge protection circuit 102 is provided between the external connection pad 101 and the output circuit 103, and includes a PMIS transistor 105, an NMIS transistor 106, a first resistor 107 and a second resistor 108. The PMIS transistor 105 includes a source connected to a power supply line 119 for supplying a power supply voltage VDD, a gate connected to the power supply line 119 via the first resistor 107, a drain connected to the external connection pad 101, and a substrate region (n well) connected to the power supply line 119. Moreover, the NMIS transistor 106 includes a source connected to a ground line 120 for supplying a ground voltage VSS, a gate connected to the ground line 120 via the second resistor 108, a drain connected to the external connection pad 101, and a substrate region (p well) connected to the ground line 120.
The output circuit 103 is provided between the electrostatic discharge protection circuit 102 and the output pre-buffer circuit 104, and includes a PMIS transistor 111 and an NMIS transistor 112. The PMIS transistor 111 includes a source connected to the power supply line 119, a gate connected to an output terminal of a first pre-buffer 115 of the output pre-buffer circuit 104, a drain connected to the external connection pad 101, and a substrate region (n well) connected to the power supply line 119. Moreover, the NMIS transistor 112 includes a source connected to the ground line 120, a gate connected to an output terminal of a second pre-buffer 117 of the output pre-buffer circuit 104, a drain connected to the external connection pad 101, and a substrate region (p well) connected to the ground line 120.
The output pre-buffer circuit 104 for amplifying an output signal from the internal circuit 121 is provided between the internal circuit 121 and the output circuit 103, and includes a first pre-buffer circuit 116 that includes the first pre-buffer 115 in the last stage and a second pre-buffer current 118 that includes the second pre-buffer 117 in the last stage. The first pre-buffer 115 includes a power supply voltage terminal connected to the power supply line 119, a ground terminal connected to the ground line 120, an output terminal connected to the gate of the PMIS transistor 111 of the output circuit 103, and an input terminal connected to the internal circuit 121. Moreover, the second pre-buffer 117 includes a power supply voltage terminal connected to the power supply line 119, a ground terminal connected to the ground line 120, an output terminal connected to the gate of the NMIS transistor 112 of the output circuit 103, and an input terminal connected to the internal circuit 121. Note that the first pre-buffer circuit 116 and the second pre-buffer current 118 each include a plurality of pre-buffers according to the degree of amplification by which an output signal from the internal circuit 121 is to be amplified. The first and second pre-buffer circuits 116 and 118 are configured so that two high and low output signals or two identical output signals are output from the output terminal of the first pre-buffer 115 in the last stage in the first pre-buffer circuit 116 and from the output terminal of the second pre-buffer 117 in the last stage in the second pre-buffer current 118.
With the conventional semiconductor integrated circuit device having such a configuration, a surge applied between the power supply line 119 and the external connection pad 101 is absorbed by the breakdown of the PMIS transistor 105, and a surge applied between the ground line 120 and the external connection pad 101 is absorbed by the breakdown of the NMIS transistor 106. Thus, it is possible to effectively protect the output circuit 103 from a surge entering from the outside through the external connection pad 101.
Incidentally, a semiconductor integrated circuit device needs to meet an ESD test standard because it is required to assure the user of a certain surge breakdown withstand voltage. In recent years, a human body model (HBM) ESD test standard such as an MIL standard has become the global standard as an ESD test standard, and a semiconductor integrated circuit device needs to meet the HBM test standard.
FIG. 8A is a circuit diagram illustrating an evaluation circuit for conducting an ESD test based on the HBM test standard, and FIG. 8B is a waveform diagram illustrating HBM discharge waveform specifications of the MIL standard.
As illustrated in FIG. 8A, the evaluation circuit includes a charging power supply 150 and a discharging resistor 153 having a resistance of R=1.5 kxcexa9, which are arranged respectively in two circuits (the left-side circuit and the right-side circuit illustrated in FIG. 8A), which are arranged in parallel with respect to a charging/discharging capacitor 151 having a capacitance of C=100 pF. A selector switch 152 is connected to one electrode of the charging/discharging capacitor 151, and the selector switch 152 is used to selectively connect the one electrode of the charging/discharging capacitor 151 either to a high-voltage portion of the variable-voltage charging power supply 150 or to the discharging resistor 153. Moreover, the other electrode of the charging/discharging capacitor 151 is connected to a low-voltage portion of the charging power supply 150 in the left-side circuit illustrated in FIG. 8A, and is connected to the discharging resistor 153 in the right-side circuit illustrated in FIG. 8A. Then, a subject device 154 is placed in the right-side circuit illustrated in FIG. 8A between the other electrode of the charging/discharging capacitor 151 and the discharging resistor 153 so as to conduct an ESD test on the subject device 154.
In the ESD test using the evaluation circuit, one electrode of the charging/discharging capacitor 151 is first connected to the charging power supply 150 by using the selector switch 152. Then, the left-side circuit illustrated in FIG. 8A becomes a closed circuit, and the charging/discharging capacitor 151 is charged by the charging power supply 150 so that the charged voltage thereof is 4000 V, for example. Then, the electrode of the charging/discharging capacitor 151 is switched to the discharging resistor 153 by using the selector switch 152. Then, the right-side circuit illustrated in FIG. 8A becomes a closed circuit, and the charge stored in the charging/discharging capacitor 151 is applied to the subject device 154, which is a semiconductor integrated circuit device, via the discharging resistor 153.
The test is conducted based on the HBM discharge waveform specifications as illustrated in FIG. 8B. In FIG. 8B, the horizontal axis represents the stress application time, the vertical axis represents the surge current (A), Tr denotes the rise time (ns), and Td denotes the attenuation time (ns).
In the conventional semiconductor integrated circuit device illustrated in FIG. 7, the power supply voltage VDD and the ground voltage VSS are connected to the power supply line 119 and the ground line 120, respectively, during normal use. On the other hand, the ESD test based on the HBM test standard is conducted while the power supply line 119 is in an open state with its potential being unfixed, and the ground line 120 is fixed to the ground voltage VSS. Thus, in the right-side circuit of the evaluation circuit illustrated in FIG. 8A, the voltage between the two electrodes of the charging/discharging capacitor 151 is applied to the discharging resistor 153 and the semiconductor integrated circuit device (subject device 154). At this time, a voltage that has been lowered by the discharging resistor 153 is applied to the external connection pads of the input circuit and the output circuit (the input circuit and the external connection circuit of the input circuit are not shown). Note that a positive or negative charge is applied to the external connection pad 101 of the output circuit illustrated in FIG. 7, and it is determined whether the ESD standard is satisfied.
However, when the conventional semiconductor integrated circuit device illustrated in FIG. 7 is subjected to an ESD test based on the HBM test standard (Vss ground), the NMIS transistor 112 of the output circuit 103 may be locally damaged, and the withstand voltage thereof may decrease.
It is believed that the damage to the NMIS transistor 112 and the decrease in the withstand voltage thereof occur due to the following reason.
When a positive charge is applied to the external connection pad 101 while the power supply line 119 is in an open state and the ground line 120 is fixed to the voltage Vss, the p-n junction between the drain region and the substrate region of the PMIS transistor 105 becomes a parasitic forward diode 109, and the p-n junction between the drain region and the substrate region of the PMIS transistor 111 becomes a parasitic forward diode 113, in the circuit extending from the external connection pad 101 to the power supply line 119. On the other hand, in the circuit extending from the external connection pad 101 to the ground line 120, the p-n junction between the drain region and the substrate region of the NMIS transistor 106 becomes a parasitic reverse diode 110, and the p-n junction between the drain region and the substrate region of the NMIS transistor 112 becomes a parasitic reverse diode 114.
Therefore, the positive charge applied to the external connection pad 101 flows into the power supply line 119 through the parasitic forward diodes 109 and 113 to increase the potential of the power supply line 119, thereby increasing the potential of the power supply voltage terminal of the second pre-buffer 117. At this time, while the gate potential of the NMIS transistor 106 of the electrostatic discharge protection circuit 102 is fixed to the ground potential, the gate potential of the NMIS transistor 112 of the output circuit 103 is in an uncertain state. Therefore, as the potential of the power supply voltage terminal of the second pre-buffer 117 increases, the NMIS transistor 112 is turned ON before the NMIS transistor 106 is turned ON, whereby an electrostatic discharge current (surge current) flows locally through the NMIS transistor 112. It is believed that this is the cause of the local damage to the NMIS transistor 112 and the decrease in the withstand voltage thereof.
An object of the present invention is to provide a semiconductor integrated circuit device including an electrostatic discharge protection circuit with an ESD protection capability that satisfies the requirements in a surge test based on the HBM test standard.
A first semiconductor integrated circuit device of the present invention includes: an external connection pad; an electrostatic discharge protection circuit connected to the external connection pad; an output circuit connected to the external connection pad; an output pre-buffer circuit connected to the output circuit; a first power supply line for supplying a power supply voltage to the electrostatic discharge protection circuit and the output circuit; and a second power supply line for supplying a power supply voltage to the output pre-buffer circuit, wherein the first power supply line and the second power supply line are electrically separated from each other.
Thus, the first power supply line for supplying the power supply voltage to the electrostatic discharge protection circuit and the output circuit and the second power supply line for supplying the power supply voltage to the output pre-buffer circuit are electrically separated from each other, whereby the potential of the second power supply line will not be increased by the application of a positive charge to the external connection pad during an ESD test. Therefore, the activation of an element in the output pre-buffer circuit is suppressed, thereby suppressing the early activation of a certain element, prior to the activation of others, in the output circuit due to the activation of the element in the output pre-buffer circuit. Thus, it is possible to suppress a surge breakdown due to a localized current flow to the certain element in the output circuit, and it is possible to obtain a semiconductor integrated circuit device having a high surge withstand voltage.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: an input buffer circuit connected to the external connection pad; and a protection resistor provided between the external connection pad and the input buffer circuit. In this way, the electrostatic discharge protection circuit can function as a protection circuit for the output circuit and the input buffer circuit.
In one embodiment of the present invention: the electrostatic discharge protection circuit includes a first PMIS transistor and a first NMIS transistor, the first PMIS transistor including a source connected to the first power supply line, a drain connected to the external connection pad and an n-type substrate region connected to the first power supply line, and the first NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad and a p-type substrate region connected to the ground line; the output pre-buffer circuit includes a first pre-buffer circuit and a second pre-buffer circuit, the first pre-buffer circuit including, in a last stage, a first pre-buffer whose power supply terminal is connected to the second power supply line, and the second pre-buffer circuit including, in a last stage, a second pre-buffer whose power supply terminal is connected to the second power supply line; and the output circuit includes a second PMIS transistor and a second NMIS transistor, the second PMIS transistor including a source connected to the first power supply line, a drain connected to the external connection pad, a gate connected to an output terminal of the first pre-buffer and an n-type substrate region connected to the first power supply line, and the second NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad, a gate connected to an output terminal of the second pre-buffer and a p-type substrate region connected to the ground line. In this way, it is possible to prevent the second NMIS transistor from being activated prior to the activation of the first NMIS transistor in response to the output from the second pre-buffer during an ESD test. Thus, it is possible to suppress a decrease in the surge withstand voltage due to a localized current flow to the second NMIS transistor.
It is preferred that the semiconductor integrated circuit device further includes: a first resistor provided between a gate of the first PMIS transistor and the first power supply line; and a second resistor provided between a gate of the first NMIS transistor and the ground line.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a third PMIS transistor including a gate connected to the ground line, a source connected to the first power supply line and a drain connected to a gate of the first PMIS transistor; a first resistor provided between the third PMIS transistor and the ground line; a third NMIS transistor including a gate connected to the first power supply line, a source connected to the ground line and a drain connected to a gate of the first NMIS transistor; and a second resistor provided between the gate of the third NMIS transistor and the first power supply line. In this way, the third PMIS transistor and the third NMIS transistor can function as resistors, whereby it is possible to reduce the area to be occupied by the semiconductor integrated circuit device.
A second semiconductor integrated circuit device of the present invention includes: an external connection pad; an electrostatic discharge protection circuit connected to the external connection pad and including an n-type substrate region; an output circuit connected to the external connection pad and including an n-type substrate region; an output pre-buffer circuit connected to the output circuit; a first power supply line for supplying a power supply voltage to the electrostatic discharge protection circuit and the output circuit; and a second power supply line for fixing a potential of the n-type substrate region of each of the electrostatic discharge protection circuit and the output circuit, wherein the first power supply line and the second power supply line are electrically separated from each other.
Thus, the first power supply line for supplying the power supply voltage to the electrostatic discharge protection circuit and the output circuit and the second power supply line for fixing the potential of the n-type substrate region are electrically separated from each other, whereby it is possible to suppress the flow of a positive charge to the first power supply line via the forward parasitic diodes of the first and second PMIS transistors upon application of a positive charge to the external connection pad during an ESD test, thus suppressing an increase in the potential of the first power supply line. Therefore, the activation of an element in the output pre-buffer circuit is suppressed, thereby suppressing the early activation of a certain element, prior to the activation of others, in the output circuit due to the activation of the element in the output pre-buffer circuit. Thus, it is possible to suppress a surge breakdown due to a localized current flow to the certain element in the output circuit, and it is possible to obtain a semiconductor integrated circuit device having a high surge withstand voltage.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: an input buffer circuit connected to the external connection pad; and a protection resistor provided between the external connection pad and the input buffer circuit. In this way, the electrostatic discharge protection circuit can function as a protection circuit for the output circuit and the input buffer circuit.
In one embodiment of the present invention: the electrostatic discharge protection circuit includes a first PMIS transistor and a first NMIS transistor, the first PMIS transistor including a source connected to the first power supply line, a drain connected to the external connection pad and the n-type substrate region connected to the second power supply line, and the first NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad and a p-type substrate region connected to the ground line; the output pre-buffer circuit includes a first pre-buffer circuit and a second pre-buffer circuit, the first pre-buffer circuit including, in a last stage, a first pre-buffer whose power supply terminal is connected to the first power supply line, and the second pre-buffer circuit including, in a last stage, a second pre-buffer whose power supply terminal is connected to the first power supply line; and the output circuit includes a second PMIS transistor and a second NMIS transistor, the second PMIS transistor including a source connected to the first power supply line, a drain connected to the external connection pad, a gate connected to an output terminal of the first pre-buffer and the n-type substrate region connected to the second power supply line, and the second NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad, a gate connected to an output terminal of the second pre-buffer and a p-type substrate region connected to the ground line. In this way, it is possible to prevent the second NMIS transistor from being activated prior to the activation of the first NMIS transistor in response to the output from the second pre-buffer during an ESD test. Thus, it is possible to suppress a decrease in the surge withstand voltage due to a localized current flow to the second NMIS transistor.
It is preferred that the semiconductor integrated circuit device further includes: a first resistor provided between a gate of the first PMIS transistor and the first power line supply; and a second resistor provided between a gate of the first NMIS transistor and the ground line.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a third PMIS transistor including a gate connected to the ground line, a source connected to the first power supply line and a drain connected to a gate of the first PMIS transistor; a first resistor provided between the third PMIS transistor and the ground line; a third NMIS transistor including a gate connected to the first power supply line, a source connected to the ground line and a drain connected to a gate of the first NMIS transistor; and a second resistor provided between the gate of the third NMIS transistor and the first power supply line. In this way, the third PMIS transistor and the third NMIS transistor can function as resistors, whereby it is possible to reduce the area to be occupied by the semiconductor integrated circuit device.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a fourth PMIS transistor including a gate connected to the first power supply line, a source connected to the external connection pad and a drain connected to the gate of the first PMIS transistor; and a fifth PMIS transistor including a gate connected to the first power supply line, a source connected to the external connection pad and a drain connected to the gate of the second PMIS transistor. In this way, it is possible to reliably keep the first and second PMIS transistors OFF, whereby even when a high voltage is applied to the external connection pad during an ESD test, it is possible to suppress the movement of a positive charge to the first power supply line through the first and second PMIS transistors. Thus, the effects as described above can be realized more reliably.
A third semiconductor integrated circuit device of the present invention includes: an external connection pad; an electrostatic discharge protection circuit connected to the external connection pad and including an n-type substrate region; an output circuit connected to the external connection pad and including an n-type substrate region; an output pre-buffer circuit connected to the output circuit; a power supply line for supplying a power supply voltage to the electrostatic discharge protection circuit, the output circuit and the output pre-buffer circuit; and a substrate-potential-fixing PMIS transistor for fixing a potential of the n-type substrate region of each of the electrostatic discharge protection circuit and the output circuit, the substrate-potential-fixing PMIS transistor including a gate connected to the external connection pad, a source connected to the power supply line and a drain connected to the n-type substrate region of each of the electrostatic discharge protection circuit and the output circuit.
In this way, even if a parasitic forward diode is formed with the n-type substrate region of each of the electrostatic discharge protection circuit and the output circuit being one pole upon application of a positive charge to the external connection pad in an ESD test, the substrate-potential-fixing PMIS transistor is turned OFF upon application of a positive charge to the external connection pad since the gate of the substrate-potential-fixing PMIS transistor is connected to the external connection pad. Therefore, it is possible to suppress an increase in the potential of the power supply line due to a charge flowing into the power supply line from the electrostatic discharge protection circuit or the output circuit. Therefore, the activation of an element in the output pre-buffer circuit is suppressed, thereby suppressing the early activation of a certain element, prior to the activation of others, in the output circuit due to the activation of the element in the output pre-buffer circuit. Thus, it is possible to suppress a surge breakdown due to a localized current flow to the certain element in the output circuit, and it is possible to obtain a semiconductor integrated circuit device having a high surge withstand voltage.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: an input buffer circuit connected to the external connection pad; and a protection resistor provided between the external connection pad and the input buffer circuit. In this way, the electrostatic discharge protection circuit can function as a protection circuit for the output circuit and the input buffer circuit.
In one embodiment of the present invention: the electrostatic discharge protection circuit includes a first PMIS transistor and a first NMIS transistor, the first PMIS transistor including a source connected to the power supply line, a drain connected to the external connection pad and the n-type substrate region connected to the drain of the substrate-potential-fixing PMIS transistor, and the first NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad and a p-type substrate region connected to the ground line; the output pre-buffer circuit includes a first pre-buffer circuit and a second pre-buffer circuit, the first pre-buffer circuit including, in a last stage, a first pre-buffer whose power supply terminal is connected to the power supply line, and the second pre-buffer circuit including, in a last stage, a second pre-buffer whose power supply terminal is connected to the power supply line; and the output circuit includes a second PMIS transistor and a second NMIS transistor, the second PMIS transistor including a source connected to the power supply line, a drain connected to the external connection pad, a gate connected to an output terminal of the first pre-buffer and the n-type substrate region connected to the drain of the substrate-potential-fixing PMIS transistor, and the second NMIS transistor including a source connected to a ground line, a drain connected to the external connection pad, a gate connected to an output terminal of the second pre-buffer and a p-type substrate region connected to the ground line. In this way, it is possible to prevent the second NMIS transistor from being activated prior to the activation of the first NMIS transistor in response to the output from the second pre-buffer during an ESD test. Thus, it is possible to suppress a decrease in the surge withstand voltage due to a localized current flow to the second NMIS transistor.
It is preferred that the semiconductor integrated circuit device further includes: a first resistor provided between a gate of the first PMIS transistor and the power supply line; and a second resistor provided between a gate of the first NMIS transistor and the ground line.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a third PMIS transistor including a gate connected to the ground line, a source connected to the power supply line and a drain connected to a gate of the first PMIS transistor; a first resistor provided between the third PMIS transistor and the ground line; a third NMIS transistor including a gate connected to the power supply line, a source connected to the ground line and a drain connected to a gate of the first NMIS transistor; and a second resistor provided between the gate of the third NMIS transistor and the power supply line. In this way, the third PMIS transistor and the third NMIS transistor can function as resistors, whereby it is possible to reduce the area to be occupied by the semiconductor integrated circuit device.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a fourth PMIS transistor including a gate connected to the power supply line, a source connected to the external connection pad and a drain connected to the gate of the first PMIS transistor; and a fifth PMIS transistor including a gate connected to the power supply line, a source connected to the external connection pad and a drain connected to the gate of the second PMIS transistor. In this way, it is possible to reliably keep the first and second PMIS transistors OFF, whereby even when a high voltage is applied to the external connection pad during an ESD test, it is possible to suppress the movement of a positive charge to the power supply line through the first and second PMIS transistors. Thus, the effects as described above can be realized more reliably.
In one embodiment of the present invention, the semiconductor integrated circuit device further includes: a first time-constant-adjusting resistor provided between the gate of the fourth PMIS transistor and the power supply line; a first potential-fixing capacitor having one pole connected to the gate of the fourth PMIS transistor and the other pole connected to the ground line; a second time-constant-adjusting resistor provided between the gate of the fifth PMIS transistor and the power supply line; and a second potential-fixing capacitor having one pole connected to the gate of the fifth PMIS transistor and the other pole connected to the ground line. In this way, the gate voltage of each of the fourth and fifth PMIS transistors is held at a low potential from the beginning of an ESD test, whereby the first and second PMIS transistors can be kept OFF reliably by the fourth and fifth PMIS transistors. Thus, the effects as described above can be realized more reliably.